+ Available for free, including all source code. + Short learning curve making it suitable for student design courses. + Hierarchical (full-custom-like) layout style on sea-of-gates. + Powerful tools for placement, routing, simulation and extraction. + Any combination of automatic and interactive manual layout. + OCEAN can handle even the largest designs. + Running on Sun workstations and Linux PC's, easy installation. + Includes three sea-of-gates images with libraries and a 200,000 transistor sea-of-gates chip. + Can be easily adapted to arbitrary images with any number of layers. + Interface programs for other tools and systems (SIS, Cadence, etc.) + Elaborate Users Manual with hands-on tutorials. + Robust and "combat-proven", used by hundreds of people.
* Sun Sparc * 386, 486 and Pentium PCThe minimum requirement is that the computer runs UNIX (or LINUX for PC) with X-window release 11.3 or higher. A disk space of about 50 Megabyte is required for installation.
* source code (C/C++) of all tools * executables for 3 popular hardware platforms * cell libraries for 3 different semi-custom images * full documentation with hands-on tutorial examples * conversion tools for SIS, Cadence. * much more.You can retrieve OCEAN and additional documentation with the SPACE distribution via:
The SPACE website: www.space.tudelft.nl (goto the Download menu)We advise to retrieve first the documents with the user manual. Click here for the on-line users manual. A PostScript version of the users manual is avaialble in the distribution. If you have any questions, remarks or problems, just contact us:
The SPACE Support Team, Circuits and Systems Section, Department of Micro Electronics, Faculty for Electrical Engineering, Mathemathics and Computer Science, Delft University of Technology, Mekelweg 4, 2628 CD Delft, The Netherlands. Phone: +31-15-2786232 (Simon de Graaf) Phone: +31-15-2786217 (Arjan van Genderen) Phone: +31-15-2786258 (Nick van der Meijs) Email: email@example.comClick here for the release list.
* Run logic synthesis tools and enter the circuit in various formats. Convenient input from logical synthesis tools (e.g SIS, MIS). SLS-network format for textual circuit entry. Edif circuit interface. * Interactively simulate this circuit at logic level, switch-level and SPICE. The simulator interface has the unique capability to switch the simulation level just at the stroke of a button. Graphical input simulation stimuli. A very powerful and fast switch-level simulator is included. * Create hierarchical layouts of hierarchical circuits. In contrast to other sea-of-gates and gate-array systems, the circuit hierarchy does not have to be flattened. You can use and create modules of any shape and size. Complexity can be handled effectively. OCEAN can handle very large layouts. * Automatically place and route. The state-of-the-art placer and router are simply started by the touch of a button from the layout interface. Both the placer and the router make efficiently use of the unused space in the sub- modules. Any number of interconnect layers can be handled. Manual pre-routing of critical nets, special power and clock routing facilities enable high-performance designs. Many special provisions for semi-custom layout (e.g. substrate contacts, power rails connection) are supported. Unused transistors can be automatically converted into capacitances for power decoupling. * Manually place, route, view and modify the layout. The interactive layout interface give a easy control over any combination of automatic and manual design. For example, you can make part of a wire, and just click a button to make the automatic router finish the rest of it. Mask-level layout (polygons) is displayed. Very fast graphics for even the largest layout (2,000,000 boxes). * Verify the connectivity and correctness of the layout design. Any short-circuits and unconnects are indicated in the layout. * Perform design rule checking and layout purification of manual layouts. Objects are snapped to the grid. Stacked vias are indicated. * Extract the circuit back from the layout. An advanced layout to circuit extractor is included, which is capable of extracting accurate parasitics. * Interactively simulate the extracted circuit on three levels of accuracy. Easy comparison with the original circuit. * Perform this fast and convenient design cycle as many times as necessary.
1. fishbone (gate-isolation image in double metal process) 2. octagon (symmetrical and rotatable image in 3 metal layer process) 3. gatearray (old fashioned row-based gate-array in single-layer process)Adding your own image, library and technology description is easy. OCEAN can handle any number of interconnect layers and intricate image structures. The basic library allows you to create digital as well as analog designs. The layout of an entire 200,000 transistor chip in the fishbone image is included with OCEAN.
1. Minimization of the fabrication time. Because the chips are prefabricated (the transistors are already on the master image), the silicon foundry only processes the masks related to metal wires. 2. Minimization of the design time. The time involved in designing a cell layout is reduced dramatically (as compared to full-custom) because the transistors are preplaced on the image. Typically, it takes only a few minutes to layout a flipflop or a combinatorial gate, and the designer does not need to know anything about the process design rules. 3. Minimization of the chip cost. The layout design starts with a prefabricated master image. This is a semi-manufactured article that can be produced in large quantities. At Delft University of Technology we have 150 wafers for the fishbone image in stock. 4. Full-custom properties on Semi-Custom chips: Efficient implementation of structured logic (RAM, PLA etc.). In contrast to the conventional gate-array, a sea-of-gates does not have pre-defined routing channels. This enables a much more compact and clean implementation of structured circuits such as processors.The OCEAN suite of tools handles a wide variety of sea-of-gates master images and process technologies. The tools madonna (the placer), trout (the router) and fish (purifier and design rule checker) handle the various peculiarities of the images to produce optimal layout.
cedif Write EDIF netlist format. csls Write SLS netlist format. fish Layout purifier for sea-of-gates, DRC. ghoti Circuit purifier for spice. madonna Automatic placer. seadali Interactive layout editor, general interface for automatic and manual layout generation. simeye Interactive simulator interface, enables unequaled smooth work with sls and spice. sls Logic level and switch-level simulator. space Fast & accurate layout extractor. trout Automatic router, connectivity verifier. xedif Read EDIF netlist format. xsls Read SLS netlist format.