personal profile René van Leuken

Associate Professor

Expertise: High-level VLSI system design

Themes: High-level Electronic (VLSI) System Level Design

Contact details

Group: Circuits and Systems (CAS)
Department of Microelectronics
Room:HB 17.260
Phone:+31-15-27 86696
Personal webpage

List of publications

Rene van Leuken is a staff member at CAS. His research interests include Algorithms and Architectures, ESL design, high level synthesis, VLSI design methodology, System model methodology, system modeling and optimization, VLSI System - and Complex Computing Blocks realization, with application areas including image processing and data stream processing.

He is currently involved in two EU (Catrene) funded projects:

  • COBRA: Computing Fabric for High Performance Applications
  • H-INCEPTION: Heterogeneous Inception

Workshop and Journal Reviewer

DAC, ICCAD, ISCAS, PATMOS, MICPRO Journal Microprocessors and Microsystems, Journal of Circuits, Systems, and Computers (JCSC), Journal of Analog Integrated Circuits and Signal Processing, EURASIP Journal on Embedded Systems, General Chair PATMOS 2009, Program Chair PATMOS 2010, Guest Editor JOLPE - Journal of Low Power Electronics, Reviewer Medea projects.

Faculty Committees

Curriculum committee EE Micro-Electronics [2003], CEES Exam Committee [2004 - 2008], CE Curriculum committee [2008], CEES Education Committee [2008 - present].


ET4054 Methods and algorithms for system design

System design by logic synthesis, optimization, and combinatorial algorithms

ET4351 VLSI Systems on Chip

How to design, connect and implement large macro IP blocks that constitutes a system on chip


Computational neuroscience and bio-inspired circuits and algorithms

Low-power neuro-inspired or neuromorphic circuits and algorithms; low-power circuits and systems for neural interfacing.


Design approach for resilient integrated electronic systems in automotive and avionics applications

Computing Fabric for high performance Applications

Develop an open, flexible and high performance platform by substituting heterogeneous mixed HW/SW specialized sub-systems by application specific processor arrays.

Last updated: 23 Dec 2016