dr.ir. N.P. van der Meijs

Associate Professor
Circuits and Systems (CAS), Department of Microelectronics


Promotor:

Expertise: VLSI design verification

Themes: VLSI design verification

Biography

Nick van der Meijs received the M.Sc. Degree in Electrical Engineering (cum laude) from the Delft University of Technology in Delft, the Netherlands. In August 1985, he joined the Network Theory Section of the Department of Electrical Engineering at the Delft University of Technology, to work as a research assistant under the supervision of Prof. P.M. Dewilde. He has been an assistent professor since March 1, 1990, and an associate professor since August 1, 1998. In January 1992 he obtained his Ph.D. Degree in Electrical Engineering, the title of his thesis was "Accurate and Efficient Layout Extraction". In 1993 he received a Dfl. 2.000.000 "Pionier" (Pioneer) grant from the NWO (Netherlands Organization for Scientific Research) for research on physical modeling and verification of integrated circuits.

He has conducted research into various topics, including module generation, frameworks and physical design verification. He has contributed extensively to the design and implementation of the Nelsis/Ocean IC design system and the SPACE layout to circuit extractor. As an associate professor, he has designed and taught several courses from freshman to graduate level. Currently he teaches Introduction to Integrated Circuit Design, Circuit Theory (both freshman) and Introduction to Electronic Design Automation (undergrad). He is leading a group performing research on modeling and verification of parasitic effects in advanced integrated circuits.

His main professional interest is in the field of efficient (practical) algorithms for Electronic Design Automation and foremost in modeling and extraction of physical/electrical effects in large integrated circuits.

EE1L11 EPO-1: Booming Bass

Build, analyze and characterize a sound system consisting of a power source, amplifier and 3-way filters.

EE2C11 Integrated circuits

Analysis and design of digital integrated circuits (electronics and systems aspects)

ET4293 Digital IC design

Analysis and design of a deep-submicron VLSI subsystem with full comprehension of how its performance, power dissipation, size and reliability relates to its physical implementation.

  1. Considering Crosstalk Effects in Statistical Timing Analysis
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    IEEE Tr. Computer-Aided Design of Integrated Circuits and Systems,
    Volume 33, Issue 2, pp. 318-322, February 2014. DOI: 10.1109/TCAD.2013.2279515
    document

  2. Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver
    Qin Tang; J. Rodriguez; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    IEEE Tr. Computer-Aided Design of Integrated Circuits and Systems,
    Volume 33, Issue 2, pp. 210-223, February 2014. DOI: 10.1109/TCAD.2013.2287179
    document

  3. Dynamic Thermal Estimation Methodology for High Performance 3D MPSoC
    A. Zjajo; N.P. van der Meijs; R. van Leuken;
    IEEE Tr. Very Large Scale Integration (VLSI) Systems,
    Volume 22, pp. 1920-1933, 2014.

  4. A 0.1 pJ Freeze Vernier time-to-digital converter in 65nm CMOS
    K. Blutman; J. Angevare; A. Zjajo; N.P. van der Meijs;
    In IEEE Int. Conf. Circuits and Systems (ISCAS),
    Melbourne, Australia, IEEE, pp. 85-88, June 2014. DOI: 10.1109/ISCAS.2014.6865071
    document

  5. Statistical power optimization of deep-dubmicron digital CMOS circuits based on structured perceptron
    A. Zjajo; N. van der Meijs; R. van Leuken;
    In IEEE International Symposium on Integrated Circuits,
    Singapore, pp. pp. 1-4, 2014.

  6. Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Solver
    Qin Tang; J. Rodriguez; A. Zjajo; M. Berkelaar; N. van der Meijs;
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
    2013. in press.

  7. Considering Crosstalk Effects in Statistical Timing Analysis
    Qin Tang; A. Zjajo; M. Berkelaar; N. van der Meijs;
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
    2013. in press.

  8. Adaptive Thermal Monitoring of Deep-Submicron CMOS VLSI Circuits
    A. Zjajo; N.P. van der Meijs; R. van Leuken;
    Journal of Low Power Electronics,
    Volume 9, Issue 4, pp. 403-413, December 2013.
    document

  9. Dynamic Thermal Estimation Methodology for High Performance 3D MPSoC
    A. Zjajo; N.P. van der Meijs; R. van Leuken;
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
    2013. DOI: 10.1109/TVLSI.2013.2280667
    document

  10. A CMOS 0.23pJ Freeze Vernier Time-to-Digital Converter
    J. Angevare; K. Blutman; A. Zjajo; N.P. van der Meijs;
    In IEEE Nordic Microelectronics Conference,
    Vilnius, Lithuania, 2013. 4 pages.
    document

  11. Balanced Stochastic Truncation of Coupled 3D Interconnect
    A. Zjajo; N. van der Meijs; R. van Leuken;
    In IEEE International Conference on IC Design and Technology,
    Pavia, Italy, pp. 13-16, 2013.
    document

  12. An inspiring BSc-EE curriculum for science and engineering
    N.P. van der Meijs; M. Bartek; P. Bauer; A.J. van Genderen; G.J.M. Janssen;
    In Proc. 42-th International European Microwave Conference (EuMC-2012),
    Amsterdam, pp. 494-497, October 2012.
    document

  13. Direct Statistical Simulation of Timing Properties in Sequential Circuits
    J. Rodriguez; Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In Proceedings of PATMOS 2012,
    Newcastle upon Tyne, UK, September 2012.
    document

  14. Towards An Intrinsically Statistical SPICE-Level Simulator
    M. Berkelaar; Qin Tang; A. Zjajo; J. Rodriguez; N.P. van der Meijs;
    In Proceedings of VARI 2012,
    Sophia Antipolis, France, June 2012.
    document

  15. Crosstalk-Aware Statistical Interconnect Delay Calculation
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In Proceedings of ASPDAC 2012,
    Sydney, Australia, January 2012.
    document

  16. A 11 uW 0C-160C Temperature Sensor in 90 nm CMOS for Adaptive Thermal Monitoring of VLSI Circuits
    A. Zjajo; N.P. van der Meijs; T.G.R.M. van Leuken;
    In Proceedings of ISCAS 2012,
    Seoul, Korea, May 2012.
    document

  17. Thermal Analysis of 3D Integrated Circuits Based on Discontinous Galerkin Finite Element Method
    A. Zjajo; N.P. van der Meijs; T.G.R.M. van Leuken;
    In Proceedings of ISQED 2012,
    Santa Clara, CA, USA, March 2012.
    document

  18. A 26 uW 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios
    P.J.A. Harpe; C. Zhou; Yu Bi; N.P. van der Meijs; X. Wang; K. Philips; G. Dolmans; H. de Groot;
    IEEE J. Solid State Circuits,
    Volume 46, Issue 7, pp. 1585-1595, July 2011. 10.1109/JSSC.2011.2143870.
    document

  19. Stochastic Analysis of Deep-Submicron CMOS Process for Reliable Circuits Designs
    A. Zjajo; Qin Tang; J. Pineda de Gyvez; M. Berkelaar; A. Di Bucchianico; N.P. van der Meijs;
    IEEE Transactions on Circuits and Systems-I: Regular Papers,
    Volume 58, Issue 1, pp. 164-175, January 2011.
    document

  20. Pseudo Circuit Model for Representing Uncertainty in Waveforms
    A. Nigam; Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In Design, Automation and Test in Europe (DATE),
    Grenoble, France, March 2011.
    document

  21. Efficient Sensitivity-Based Capacitance Modeling for Systematic and Random Geometric Variations
    Yu Bi; P. Harpe; N.P. van der Meijs;
    In IEEE Asia and South Pacific Design Automation Conference, (ASP-DAC 2011),
    Yokohama, Japan, pp. 61-66, January 2011. ISBN: 978-1-4244-7516-2.
    document

  22. Fast Statistical Analysis of RC Nets Subject to Manufacturing Variabilities
    Yu Bi; K.J. van der Kolk; J.F. Villena; L.M. Silveira; N.P. van der Meijs;
    In IEEE Design, Automation and Test in Europe (DATE 2011),
    Grenoble, France, March 2011. Print ISBN: 978-1-61284-208-0, ISSN: 1530-1591.
    document

  23. Enhanced Sensitivity Computation for BEM Based Capacitance Extraction Using the Schur Complement Technique
    Yu Bi; S. de Graaf; N.P. van der Meijs;
    In IEEE Custom Integrated Circuits Conference (CICC),
    San Jose (CA), IEEE, September 2011.
    document

  24. Accuracy Consideration of a Non-Gaussian Interconnect Delay Model for Submicron CMOS Statistical Static Timing Analysis
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In IEEE International NanoElectronics Conference (INEC),
    Chang Gung University, Tao-Yuan, Taiwan, June 2011.
    document

  25. Balanced Truncation of a Stable Non-Minimal Deep-Submicron CMOS Interconnect
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In International Conference on IC Design and Technology (ICICDT),
    Kaohsiung, Taiwan, May 2011.
    document

  26. Statistical Delay Calculation with Multiple Input Simultaneous Switching
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In International Conference on IC Design and Technology (ICICDT),
    Kaohsiung, Taiwan, May 2011.
    document

  27. Adaptive Numerical Integration Methods for Deterministic Analysis of Non-Stationary Noise in Dynamic Integrated Circuits
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In Design and Technology of Integrated Systems (DTIS),
    Athens, Greece, April 2011.
    document

  28. Statistical Moment Estimation of Delay and Power in Circuit Simulation
    A. Nigam; Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    Journal of Low Power Electronics,
    Volume 6, Issue 4, December 2010. Invited Paper.
    document

  29. Stochastic Analysis of Deep-Submicron CMOS Process for Reliable Circuits Designs
    A. Zjajo; Qin Tang; J. Pineda de Gyvez; M. Berkelaar; A. Di Bucchianico; N.P. van der Meijs;
    IEEE Transactions on Circuits and Systems-I: Regular Papers,
    2010. DOI: 10.1109/TCSI.2010.2055291
    document

  30. Transistor Level Waveform Evaluation for Timing Analysis
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In European Workshop on CMOS Variability (VARI),
    Montpellier, France, May 2010. 6 pages.
    document

  31. RDE-Based Transistor-Level Gate Simulation for Statistical Static Timing Analysis
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In IEEE Design Automation Conference (DAC),
    Anaheim, California, pp. 787-792, June 2010.
    document

  32. Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS),
    Grenoble, France, September 2010.
    document

  33. Statistical Moment Estimation in Circuit Simulation
    A. Nigam; Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In European Workshop on CMOS Variability (VARI),
    Montpellier, France, May 2010.
    document

  34. Noise Analysis of Non-Linear Dynamic Integrated Circuits
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In IEEE Custom Integrated Circuits Conference (CICC 2010),
    San Jose, California, September 2010.
    document

  35. Discrete Recursive Algorithm for Estimation of Non-Stationary Noise in Deep-Submicron Integrated Circuits
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2010),
    Shanghai, China, November 2010.
    document

  36. Digital Cartesian Feedback Linearization of Switched Mode Power Amplifiers
    A. Viteri; A. Zjajo; T. Hamoen; N.P. van der Meijs;
    In 17th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2010),
    Athens, Greece, December 2010.
    document

  37. Sensitivity Computation Using Domain-Decomposition for Boundary Element Method Based Capacitance Extractors
    Yu Bi; K.J. van der Kolk; N.P. van der Meijs;
    In Proc. IEEE Custom Integrated Circuits Conference (CICC),
    San Jose (CA), IEEE, September 2009.
    document

  38. A Simplified Transistor Model for CMOS Timing Analysis
    Qin Tang; A. Zjajo; M. Berkelaar; N. van der Meijs;
    In 20th annual workshop on circuits, systems and signal processing--ProRISC,
    Veldhoven, STW, November 2009. ISBN 978-90-73461-62-8.
    document

  39. Parameterized RC extraction using SPACE
    Y. Bi; N.P. van der Meijs;
    In 20th annual workshop on circuits, systems and signal processing--ProRISC,
    Veldhoven, STW, pp. 202-207, November 2009. ISBN 978-90-73461-62-8.
    document

  40. 3D Capacitance extraction based on multi-level hierarchical Schur algorithm
    Zhifeng Sheng; P. Dewilde; N. van der Meijs;
    In 20th annual workshop on circuits, systems and signal processing--ProRISC,
    Veldhoven, STW, pp. 551-555, November 2009. ISBN 978-90-73461-62-8.
    document

  41. A Radix $2^2$ Based Parallel Pipeline FFT Processor for MB-OFDM UWB system
    Nuo Li; N.P. van der Meijs;
    In 22nd IEEE Int. SOC Conference (SOCC),
    Belfast (UK), IEEE, September 2009.

  42. Improved parallel pipeline FFT processor for MB-OFDM UWB system
    Nuo Li; N.P. van der Meijs;
    In 20th annual workshop on circuits, systems and signal processing--ProRISC,
    Veldhoven, STW, pp. 475-479, November 2009. ISBN 978-90-73461-62-8.
    document

  43. Model order reduction of large RC circuits
    N.P. van der Meijs;
    In Model order reduction: theory, research aspects and applications,
    Berlin, Springer Verlag, 2008. ISBN 978-3-540-78840-9.
    document

  44. Capacitance Sensitivity Calculation for Interconnects by Adjoint Field Technique
    Y. Bi; N.P. van der Meijs; D. Ioan;
    In 12th IEEE Workshop on Signal Propagation on Interconnects,
    Avignon, France, May 2008.
    document

  45. Sensitivity Computation of Interconnect Capacitances with respect to Geometric Parameters
    Y. Bi; K. van der Kolk; D. Ioan; N.P. van der Meijs;
    In IEEE International Conference on Electrical Performance of Electronic Packaging,
    San Jose, CA, October 2008.
    document

  46. Process variation aware modeling of interconnect capacitance
    Y. Bi; N.P. van der Meijs;
    In 19th annual workshop on circuits, systems and signal processing--ProRISC,
    Veldhoven, STW, November 2008.

  47. A circuit-formulation for the non-retarded Maxwell equations
    K.J. van der Kolk; N.P. van der Meijs;
    In 19th annual workshop on circuits, systems and signal processing--ProRISC,
    Veldhoven, STW, November 2008.

  48. Surface integrated field equations method for computing 3D static and stationary electric and magnetic fields
    Z. Sheng; N.P. van der Meijs;
    In 19th annual workshop on circuits, systems and signal processing--ProRISC,
    Veldhoven, STW, November 2008.

  49. Effects of manufacturing variability on integrated passive components
    Y. Bi; N.P. van der Meijs; W.H.A. Schilders;
    In IEEE/ProRISC workshop on Circuits, Systems and Signal Processing,
    Veldhoven (NL), IEEE, November 2007. ISBN 978-90-73461-49-9.

  50. Maxwell equations on unstructured grids using finite integration methods
    W.J. Schoenmaker; P. Meuris; E. Janssens; K.J. van der Kolk; N.P. van der Meijs; W.H.A. Schilders;
    In IEEE Proc. 12th Int. Conf. on Simulation of Semiconductor Processes and Devices (SISPAD 2007),
    Vienna (Austria), IEEE, pp. 333-336, 2007.

  51. Models for integrated components coupled with their EM Environment
    D. Ioan; W.H.A. Schilders; G. Ciuprina; N.P. van der Meijs; W.J. Schoenmaker;
    In IEEE Proc. 13th Int. Symp. on Electronmagnetic Fields in Mechatronics, Electrical and Electronic Eng. (ISEF 2007),
    Prague (Czech Rep.), IEEE, pp. 333-336, 2007.

  52. A software tool for 3D meshing of VLSI interconnect structures
    K.J. van der Kolk; N.P. van der Meijs;
    In Proc. 17th annual workshop on Circuits, Systems and Signal Processing (ProRISC),
    Veldhoven (NL), pp. 286-292, November 2006.
    document

  53. Iterative solution methods based on the hierarchically semi-separable representation
    Z. Sheng; P. Dewilde; N. van der Meijs;
    In Proc. 17th annual workshop on Circuits, Systems and Signal Processing (ProRISC),
    Veldhoven (NL), pp. 343-349, November 2006.
    document

  54. On the Implementation of a 3-Dimensional Delaunay-based Mesh Generator
    K.J. van der Kolk; N.P. van der Meijs;
    In G. Ciuprina; D. Ioan (Ed.), SCEE 2006 Book of Abstracts,
    Sinaia, RO, pp. 171-172, 2006. ISBN: 978-973-718-520-4.

  55. An Efficient Method for Substrate Impedance Extraction
    Q. Wang; N.P. van der Meijs;
    In Conference on PhD Research In Microelectronics and Electronics (PRIME 2005),
    Lausanne, CH, July 2005.

  56. Substrate resistance modeling by combination of BEM and FEM methodologies
    E. Schrik; N.P. van der Meijs;
    In Scientific computing in electrical engineering,
    Heidelberg, Springer, 2004.

  57. Statistically aware buffer planning
    G.S. Garcea; N.P. van der Meijs; K.J. van der Kolk; R.H.M.J. Otten;
    In DATE'04,
    Paris, pp. 1402-1403, February 2004.
    document

  58. Throughput driven unidirectional bus design for NoC applications
    G. Garcea; N.P. van der Meijs;
    In Prorisc'04,
    Veldhoven, November 2004.

  59. Combined BEM/FEM vs. 3D FEM substrate resistance modeling
    E. Schrik; N.P. van der Meijs;
    In Prorisc'04,
    Veldhoven, November 2004.

  60. SPACE for Substrate Resistance Modeling
    N. P. van der Meijs;
    In Kluwer Book on Substrate Coupling,
    Kluwer, 2003.
    document

  61. Comparing Two Y$\Delta$ Based Methodologies for Realizable Model Reduction
    E. Schrik; N. P. van der Meijs;
    In ProRISC IEEE 14th Annual Workshop on Circuits, Systems and Signal Processing,
    November 2003.
    document

  62. Coherent Interconnect/Substrate Modeling Using SPACE - An Experimental Study
    E. Schrik; A.J. van Genderen; N.P. van der Meijs;
    In Proc. of the 33rd European Solid-State Device Research Conf.,
    Estoril, Portugal, pp. 585 -- 588, September 2003.
    document

  63. Partial Inductance Extraction with an Exponentially Damped Potential Compared to Virtual Screening
    A.J. Dammers; N.P. van der Meijs;
    In Proc. 6th IEEE workshop on Signal Propagation on Interconnects,
    Castelvecchio Pascoli - Pisa, Italy, IEEE, pp. 29-32, May 2002.
    document

  64. Combined BEM/FEM Substrate Resistance Modeling
    E. Schrik; N.P. van der Meijs;
    In Proc. 39th Design Automation Conference,
    New Orleans, LA, pp. 771-776, June 2002.
    document

  65. Substrate Resistance Modeling by Combination of BEM and FEM Methodologies
    E. Schrik; N.P. van der Meijs;
    In W.H.A. Schilders; S.H.M.J. Houben; E.J.W. ter Maten (Ed.), Scientific Computation in Electrical Engineering 2002,
    Eindhoven, NL, pp. 171-172, June 2002. ISBN 90-9015894-4.
    document
    poster http://cas.et.tudelft.nl/space/publications/2002/sceeposter_final.pdf

  66. Model Reduction for VLSI Physical Verification
    N.P. van der Meijs;
    In Proc. URSI General Assembly 2002,
    Maastricht, NL, International Union of Radio Science, August 2002.
    document

  67. Theoretical and Practical Validation of Combined BEM/FEM Substrate Resistance Modeling
    E. Schrik; P.M. Dewilde; N.P. van der Meijs;
    In Proc. Int. Conf. on Computer-Aided Design,
    San Jose, CA, pp. 10--15, November 2002.
    document

  68. Modeling Capactive Effects via the Substrate
    A. J. van Genderen; N. P. van der Meijs; E. Schrik;
    In ProRISC IEEE 12th Annual Workshop on Circuits, Systems and Signal Processing,
    pp. 366--370, November 2001.
    document

  69. Combined BEM/FEM Resistance Modeling of Stratified Substrates with Layout-Dependent Doping Patterns in the Top Layer
    E. Schrik; A. J. van Genderen; N. P. van der Meijs;
    In ProRISC IEEE 12th Annual Workshop on Circuits, Systems and Signal Processing,
    pp. 598--604, November 2001.
    document

  70. Assessment of 3D Interconnect Geometry at the System Level
    G. S. Garcea; N. P. van der Meijs;
    In ProRISC IEEE 12th Annual Workshop on Circuits, Systems and Signal Processing,
    pp. 361--365, November 2001.
    document

  71. Accurate and Efficient Layout Extraction
    N.P. van der Meijs;
    PhD thesis, Delft Univ. Techn., The Netherlands, 1992.
    document

  72. A data management interface to facilitate CAD/IC software exchanges
    N. van der Meijs; P. van der Wolf; I. Widya; P. Dewilde;
    In Proc. IEEE ICCD '87,
    pp. 403-406, 1987.

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Last updated: 30 Apr 2019