dr. Qin Tang

PhD student
Circuits and Systems (CAS), Department of Microelectronics

PhD thesis (Apr 2013): Transistor-Level Statistical Timing Analysis: Solving Random Differential Equations Directly
Promotor: Edoardo Charbon, Nick van der Meijs

Expertise: Statistical modeling of circuits

Themes: VLSI design verification

Biography

Qin Tang was a PhD student in the CAS group, with dr. Nick van der Meijs. She obtained the Ph.D degree in electronic engineering at Delft University of Technology with 20 academic publications, including top journals (TCAD/TCAS) and top conferences (DAC/DATE/ASPDAC). Ph.D research fields are mainly in statistical modeling, circuit variability, simulation software development and algorithm design. Supervised three master students, and two out of three graduated with Cum Laude.

Publications

  1. Considering Crosstalk Effects in Statistical Timing Analysis
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    IEEE Tr. Computer-Aided Design of Integrated Circuits and Systems,
    Volume 33, Issue 2, pp. 318-322, February 2014. DOI: 10.1109/TCAD.2013.2279515
    document

  2. Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver
    Qin Tang; J. Rodriguez; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    IEEE Tr. Computer-Aided Design of Integrated Circuits and Systems,
    Volume 33, Issue 2, pp. 210-223, February 2014. DOI: 10.1109/TCAD.2013.2287179
    document

  3. Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Solver
    Qin Tang; J. Rodriguez; A. Zjajo; M. Berkelaar; N. van der Meijs;
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
    2013. in press.

  4. Considering Crosstalk Effects in Statistical Timing Analysis
    Qin Tang; A. Zjajo; M. Berkelaar; N. van der Meijs;
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
    2013. in press.

  5. Transistor-level statistical timing analysis - Solving random differential equations directly
    Qin Tang;
    PhD thesis, TU Delft, Fac. EEMCS, April 2013.

  6. Direct Statistical Simulation of Timing Properties in Sequential Circuits
    J. Rodriguez; Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In Proceedings of PATMOS 2012,
    Newcastle upon Tyne, UK, September 2012.
    document

  7. Towards An Intrinsically Statistical SPICE-Level Simulator
    M. Berkelaar; Qin Tang; A. Zjajo; J. Rodriguez; N.P. van der Meijs;
    In Proceedings of VARI 2012,
    Sophia Antipolis, France, June 2012.
    document

  8. New Statistical Timing Analysis Method Considering Process Variations and Crosstalk
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van de Meijs;
    In Proceedings of VAMM 2012,
    Dresden, Germany, March 2012.
    document

  9. New Statistical Timing Analysis Method Considering Process Variations and Crosstalk
    Qin Tang;
    In Ph.D. forum of DATE 2012,
    Dresden, Germany, March 2012.

  10. Transistor-Level Gate Model Based Statistical Timing Analysis Considering Correlations
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van de Meijs;
    In Proceedings of DATE 2012,
    Dresden, Germany, March 2012.
    document

  11. Crosstalk-Aware Statistical Interconnect Delay Calculation
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In Proceedings of ASPDAC 2012,
    Sydney, Australia, January 2012.
    document

  12. Stochastic Analysis of Deep-Submicron CMOS Process for Reliable Circuits Designs
    A. Zjajo; Qin Tang; J. Pineda de Gyvez; M. Berkelaar; A. Di Bucchianico; N.P. van der Meijs;
    IEEE Transactions on Circuits and Systems-I: Regular Papers,
    Volume 58, Issue 1, pp. 164-175, January 2011.
    document

  13. Pseudo Circuit Model for Representing Uncertainty in Waveforms
    A. Nigam; Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In Design, Automation and Test in Europe (DATE),
    Grenoble, France, March 2011.
    document

  14. Voltage Sensitivity Calculation for ViVo-based Gate Models Considering Process Variations
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van de Meijs;
    In ICT.OPEN,
    Veldhoven, the Netherlands, November 2011.
    document

  15. Accuracy Consideration of a Non-Gaussian Interconnect Delay Model for Submicron CMOS Statistical Static Timing Analysis
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In IEEE International NanoElectronics Conference (INEC),
    Chang Gung University, Tao-Yuan, Taiwan, June 2011.
    document

  16. Balanced Truncation of a Stable Non-Minimal Deep-Submicron CMOS Interconnect
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In International Conference on IC Design and Technology (ICICDT),
    Kaohsiung, Taiwan, May 2011.
    document

  17. Statistical Delay Calculation with Multiple Input Simultaneous Switching
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In International Conference on IC Design and Technology (ICICDT),
    Kaohsiung, Taiwan, May 2011.
    document

  18. Adaptive Numerical Integration Methods for Deterministic Analysis of Non-Stationary Noise in Dynamic Integrated Circuits
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In Design and Technology of Integrated Systems (DTIS),
    Athens, Greece, April 2011.
    document

  19. Statistical Moment Estimation of Delay and Power in Circuit Simulation
    A. Nigam; Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    Journal of Low Power Electronics,
    Volume 6, Issue 4, December 2010. Invited Paper.
    document

  20. Stochastic Analysis of Deep-Submicron CMOS Process for Reliable Circuits Designs
    A. Zjajo; Qin Tang; J. Pineda de Gyvez; M. Berkelaar; A. Di Bucchianico; N.P. van der Meijs;
    IEEE Transactions on Circuits and Systems-I: Regular Papers,
    2010. DOI: 10.1109/TCSI.2010.2055291
    document

  21. Transistor Level Waveform Evaluation for Timing Analysis
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In European Workshop on CMOS Variability (VARI),
    Montpellier, France, May 2010. 6 pages.
    document

  22. RDE-Based Transistor-Level Gate Simulation for Statistical Static Timing Analysis
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In IEEE Design Automation Conference (DAC),
    Anaheim, California, pp. 787-792, June 2010.
    document

  23. Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations
    Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS),
    Grenoble, France, September 2010.
    document

  24. Statistical Moment Estimation in Circuit Simulation
    A. Nigam; Qin Tang; A. Zjajo; M. Berkelaar; N.P. van der Meijs;
    In European Workshop on CMOS Variability (VARI),
    Montpellier, France, May 2010.
    document

  25. Noise Analysis of Non-Linear Dynamic Integrated Circuits
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In IEEE Custom Integrated Circuits Conference (CICC 2010),
    San Jose, California, September 2010.
    document

  26. Discrete Recursive Algorithm for Estimation of Non-Stationary Noise in Deep-Submicron Integrated Circuits
    A. Zjajo; Qin Tang; M. Berkelaar; N.P. van der Meijs;
    In IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2010),
    Shanghai, China, November 2010.
    document

  27. A Simplified Transistor Model for CMOS Timing Analysis
    Qin Tang; A. Zjajo; M. Berkelaar; N. van der Meijs;
    In 20th annual workshop on circuits, systems and signal processing--ProRISC,
    Veldhoven, STW, November 2009. ISBN 978-90-73461-62-8.
    document

BibTeX support

Last updated: 8 Nov 2014

Qin Tang

Alumnus
  • Left in 2013
  • Now: State Key Laboratory of Solid State Lighting (Changzhou)
  • Personal webpage