MSc thesis project proposal

COBRA: 3D and Many ASIP core platform(s)

Hardwired SoC architectures suffer from a lack of flexibility regarding market evolution, resulting in an excessive design cycle time and increased cost. Furthermore, process variability is not yet well addressed for 40/28 nm and beyond.

The objective of COBRA is to develop and experiment an open, flexible and high performance platform by substituting heterogeneous hardware/software sub-systems by a regular array of ASIP processors. The platform will be driven by Telecom, Video, Health and Multimedia benchmark applications and demonstrated on 40/28nm silicon with 3D stacking. This massively parallel computing fabric will also improve manufacturability and energy efficiency of new Systems On Chip, due to its design regularity, while at the same time maximising flexibility by allowing software product derivatives to be generated. Software product derivatives will reduce development and manufacturing costs as well as Time-to-market when compared with hardwired alternatives.

We are looking for students to work on the RVEX VLIW processor; Project 1 is the implementation of a RVEX configuration in UMC 65nm technology (chip design). Project 2 is the re-implementation of a RVEX configuration in SystemC or C language; The goal is to have a high level (generic) version which can be simulated efficiently (eg. can run Linux) and can be synthesized into a FPGA.

Contact

dr.ir. René van Leuken

Signal Processing Systems Group

Department of Microelectronics

Last modified: 2017-12-13