Clock tree synthesis

Synchronous digital integrated circuits always contain one or more clock networks, that feed clock signals to the memory elements (flipflops, latches, memory blocks) on the chip. The problem is that such clock networks need to feed hundreds of thousands such memory elements spread out all over the chip, with very strict timing requirements. The simplest case is that the clock needs to arrive at every endpoint at exactly the same time. Given that modern deep-submicron IC technologies show a very large variation in the properties of wires and transistors, and hence in the delay of these elements, it is becoming increasingly difficult to design clock networks that have the desired timing properties under all circumstances,

The main topics of development in this area currently are: novel robust clock network structures, synthesis and analysis of regular clock structures like clock meshes / clock rings, low power clock structures, etc.

Contact

dr.ir. Nick van der Meijs

Signal Processing Systems Group

Department of Microelectronics

Last modified: 2019-04-24