ET4351 VLSI Systems on Chip

Topics: How to design, connect and implement large macro IP blocks that constitutes a system on chip
In this course, we venture to design a system on chip, where large IP blocks are available. The design problem to be solved is how to design, connect and implement these large macro IP blocks, in the "best" possible way, i.e. in terms of speed, bandwidth, power consumption and data reliability.

Topics covered among other low power optimization and reduction techniques, SoC design methodology, modeling, specification and implementation, communication architecture and protocols. Modern design starts from a C-based description (System-C) or behavior description through synthesis tools to an FPGA implementation. This course will introduce the SystemC language, SystemC-AMS and SystemC-TLM. High level modeling concepts using VHDL will be presented, as well as an introduction to synthesizable VHDL and loop optimization.

The lectures are mainly a general introduction and include a discussion and demonstration of the design tools. The students will start using the tools by means of a well-defined student design project that uses part (or all) of the design path. Some digital circuits (basic structures) are being studied as examples.

Study Goals

The aim of the course is to address some important aspects of Systems on Chip (SoC) design: Including: 1) Algorithm to specification 2) Low power digital design issues, 3) On-chip system IP high level interconnect issues, 4) Hardware and software interaction issues

Teachers

dr.ir. René van Leuken

High-level VLSI system design

ir. Alexander de Graaf

High-level VLSI design, System-C

Last modified: 2019-02-07

Details

Credits: 4 EC
Period: 0/0/0/3
Contact: René van Leuken